----------------------------------------------------------------------------------
-- Company: 		 Johns Hopkins University
-- Engineer: 		 Kevin Green
-- 
-- Create Date:    00:34:50 11/30/2011 
-- Design Name:    lut_3
-- Module Name:    lut_3 - RTL 
-- Project Name:   top_gillis_green
-- Target Devices: 
-- Tool versions: 
-- Description:    This is the 3-bit look-up table.  Given a the black and white
--                 vector and player, an output vector with the possible valid
--                 moves is generated.
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lut_3 is
    Port ( black : in  STD_LOGIC_VECTOR (7 downto 0);
           white : in  STD_LOGIC_VECTOR (7 downto 0);
           player : in  STD_LOGIC;
           data_out : out  STD_LOGIC_VECTOR (7 downto 0));
end lut_3;

architecture RTL of lut_3 is

begin

process(player, black, white) is
begin
		case player & black & white is
			when '0' & x"0102" => data_out <= x"04";
			when '1' & x"0201" => data_out <= x"04";
			when '1' & x"0204" => data_out <= x"01";
			when '0' & x"0402" => data_out <= x"01";
			when others => data_out <= x"00";
		end case;
end process;


end RTL;

